PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 3.0 operates at 2.5Gbps, 5Gbps and 8Gbps, and for SATA3 at 1.5Gbps, 3.0Gbps and 6Gbps. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 8Gbps.

The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

• Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
• Compact form factor – 0.165 mm2 active silicon area per lane including ESD
• Industry leading low power – typically 6.5 mW/Gbps including termination
• Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE
• Finely configurable driver impedance, amplitude and 3-tap FFE
• Supports PCIe L1 sub-states and all power-down modes, bifurcation, lane/link powerdown, SRNS, SRIS
• Minimal latency – 3 UI between parallel transfer and serial transmission
• Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
• Test support features such as ac-JTAG, near-end loopback, reverse loopback, PRBS generator + checker, PLL bypass modes, etc.
• 2D Eye Monitoring capability
• PIPE Compliant PCS with programmable PIPE frequencies
• Supports industry standard third-party controllers for PCIe, and SATA controllers via external PCS
• Protocol-compatible features such as Tx detect Rx, LOS, squelch, independent Tx/Rx rate, power modes, etc.
• Low pin-count and suitable for a variety of flip-chip and wire-bond packages
• Metallization scheme and pad/bump structures customizable to specifications