MRDIMM DDR5 & DDR5/4 PHY & Controller

The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices. It is optimized for low-power and high-speed applications with robust timing and small silicon area. It supports all JEDEC DDR5/4 SDRAM components in the market. The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

The’s comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.

• Supports DDR5 MRDIMMs, standard DDR5/4 LRDIMMs/RDIMMs/UDIMMs and standard DDR5/4 signaling, rates from 20Mbps up to 9600Mbps (MRDIMM DDR5)
• x16/x32/x64/x72/x80 data bus width extendable, supporting both MRDIMM and standard DDR5/4 DIMMs, or standard DDR5/4 SDRAM devices
• 1.2V(DDR4)/1.1V(DDR5) JEDEC I/O standard, supporting 1.2V POD_12 and 1.1V POD_11 I/Os
• Supports DDR5 dual channel mode, dual 32-bits data +8-bits ECC
• Supports CA training, CS training, and write leveling training modes
• Supports Write FFE and Read DFE equalization:
  • 1-tap FFE
  • 6-/4-tap DFE
• Both Read and Write Per bit de-skew support
• Supports multiple types of training modes for stable working: CA/CS Training, Write Leveling, DQS Gate Training, ZQ Calibration, Read/Write Training, Rx/Tx Vref Training, QCS/QCA Training for DDR5 RDIMM/LRDIMM/MRDIMM, MREP/DWL/MRD/MWD Training for DDR4 LRDIMM, MRE/DWL/HWL/MRD/MWD for DDR5 LRDIMM
• PVT compensation and timing calibration for all corner reliability
• At-speed BIST for PAD and internal loopback modes
• Supports multiple DFT methods: At-speed Scan, Stuck-at Scan, Boundary Scan
• Various power-down modes for low-power including self-refresh support
• Low-jitter PLL with small area, wide input frequency range and isolated analog supply, allowing for excellent supply rejection in noisy SoC applications

• Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
• Zero risk with robust ESD architecture
• Extensive EDA tool support for various design and automation flow
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
• Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing

• Extensive documentation
• Models
• LIB
• LEF
• Place-and-route abstracts
• LVS netlist
• GDSII files