Vendor: Analog Bits Inc. Category: Multi-Protocol PHY

Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

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Overview

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PCIe 3.0 PHY operates at 2.5Gbps, 5Gbps, and 8Gbps. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

Key features

  • Industry leading low power PMA macro – 56mW per lane at 8Gbps (7mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
  • Compact form factor – 0.2 mm2 total active area per lane
  • Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
  • Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 1- tap DFE
  • Finely configurable driver impedance, amplitude and 3-tap FFE
  • Supports L1 sub-states and all power-down modes
  • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • Multi-orientation macros of 4, 8 and 16 lane SERDES are available for most common metal stacks
  • Test support features such as ac-JTAG, near-end loopback, reverse loopback, PRBS generator+checker, PLL bypass modes, etc.
  • PIPE Compliant PCS with programmable PIPE frequencies
  • Supports Bifurcation, lane/link powerdown, SRNS, SRIS
  • Supports industry standard third-party controllers for PCIe
  • Low pin-count and suitable for a variety of flip-chip packages when paired with onchip T-coils
  • Metallization scheme and pad/bump structures customizable to specifications

Silicon Options

Foundry Node Process Maturity
TSMC 28nm HPC+ —

Specifications

Identity

Part Number
Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Analog Bits Inc.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+?

Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+ is a Multi-Protocol PHY IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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