The MIPI® D-PHY TX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
- MIPI PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The MIPI® D-PHY TX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
MIPI D-PHY/LVDS Combo Receiver IP
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Allianc…
The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the sp…
AMBA AHB Bus to DDR SDRAM Controller
AMBA AHB Bus to DDR SDRAM Controller
Flash/ROM/SRAM Controller
CompactFlash/PCMCIA Host Controller with EXCA Registers
CompactFlash/PCMCIA Host Controller with EXCA Registers
DDR5/DDR4 and LPDDR5/LPDDR4 EMIF FPGA IP
DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements…
Serial Lite IV Intel® FPGA IP Core
The Serial Lite IV Intel® FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip…
R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction…
P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* conf…
Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compli…
PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 …
The HDMI Intel FPGA intellectual property (IP) core provides support for the next generation of video display interface technolog…
Ethernet is ubiquitous across many markets and applications.
Intel® FPGA IP for Ethernet Products Portfolio
Triple Speed Ethernet Triple-Speed Ethernet Intel® FPGA intellectual property (IP) supports the 10 Mbps, 100 Mbps, and 1 Gbps dat…
DisplayPort Intel® FPGA IP Core
Intel now offers a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4.
Video and Image Processing Suite
The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can u…
Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
Verification IP for DisplayPort/eDP
The Verification IP (VIP) for DisplayPort provides a comprehensive set of protocol, methodology, verification and productivity fe…