LDPC Intel® FPGA IP
Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
Overview
Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels. Intel's 5G Low-Density Parity Check (LDPC) Intel FPGA Intellectual Property (IP) core is a high-throughput encoder or decoder that is compliant with 3rd Generation Partnership Project (3GPP) 5G specification. LDPC codes offer better spectral efficiency and support the high throughput for 5G new radio (NR). With the flexibility of Intel FPGAs, various configurations can be designed and implemented and re-designed to support any changes to base graph, code rate, Z and LR width.
Features
All Decoders Have:
- MATLAB models
- Double-buffered architecture to reduce latency and boost throughput
- Early stopping criterion
- Parameters for:
- Input parallelism
- Decoding parallelism
- LLR width
- Attenuation factor
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is LDPC Intel® FPGA IP?
LDPC Intel® FPGA IP is a Channel Coding IP core from Altera listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.