The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
LIN Bus Master/Slave Controller
The LIN-CTRL core is a communication controller that transmits and receives LIN frames to perform serial communication according …
USB 2.0 Host/Device Transceiver With On-The-Go (OTG)
USB 2.0 HOST/DEVICE/OTG Transceiver is a fully integrated PHY Core which is a super-set of HOST and DEVICE PHY with High Speed (H…
The USB 2.0 embedded host controller is designed for flexibility and ease of use; is available with a Software stack; facilitates…
The USB 1.1 embedded host controller is designed for flexibility and ease of use; facilitates implementation of a wide variety of…
SMS4000 is a fully integrated CMOS transceiver compliant with IEEE 802.3z standard.
SMS3000 is a fully integrated CMOS transceiver compliant with ANSI X3T11 Fiber Channel standards.
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) an…
USB 2.0 DEVICE Transceiver is a fully integrated PHY Core which is a super-set of DEVICE PHY with High Speed (HS), Full-Speed (FS…
Dynamic Block Reed-Solomon Encoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Dynamic Block Reed-Solomon Decoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Convolutional encoding is a process of adding redundancy to a signal stream to provide error correction capability.
Turbo coding is an error correction technique widely used in the communications industry.
Turbo coding is an error correction technique widely used in the communications industry.
Distributed Arithmetic FIR (DA-FIR) Filter Generator
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP implements a configurable, multi-channel …
Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel noise back to the …
Lattice's FFT Compiler offers forward and inverse Fast Fourier Transforms for point sizes from 64 to 16384.
Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommuni…
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, de…
Single Precision IEEE-754 complete FPU
The A2F is a fully synthesizable module implemented in Verilog RTL.