Supports emerging standards for lowering cost of uncompressed HD video transport Reduce the cost of multichannel SD/HD/3G-SDI des…
- Video Transport
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Supports emerging standards for lowering cost of uncompressed HD video transport Reduce the cost of multichannel SD/HD/3G-SDI des…
The LogiCORE™ IP SDI Tx and RX Video Bridge cores are designed to interface the SDI ports of the SMPTE SDI core to the video port…
The Xilinx Processor System Reset Module design allows the customer to tailor the design to suit their application by setting cer…
Partial Reconfiguration Decoupler IP
The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs.
Partial Reconfiguration Controller
The Partial Reconfiguration Controller (PRC) IP provides management functions for Partial Reconfiguration designs.
Memory Interface is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs.
LogiCore AXI to AHB-Lite Bridge IP
Included at no additional charge with Vivado Design and System edition of software.
The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals …
IBERT for UltraScale GTY Transceivers
The customizable LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for UltraScale™ architecture GTY transceivers is des…
IBERT for UltraScale GTH Transceivers
The customizable LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for UltraScale architecture GTH transceivers is desi…
IBERT for 7 Series GTZ Transceivers
The customizable LogiCORE™ IP Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTZ transceivers is designed for eva…
The LogiCORE™ IP UltraScale™ High Speed SelectIO Wizard generates customized HDL wrappers to configures the UltraScale FPGA on-ch…
The Xilinx® HDMI solutions include HDMI TX and RX subsystems.
The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.
Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII
The Xilinx Ethernet 1G/2.5G PCS/PMA or SGMII IP LogiCORE™ provides an Ethernet Physical Coding Sublayer (PCS) with a choice of ei…
Error Correction Checking (ECC) Core
The Xilinx LogiCORE™ IP ECC core is ideal for robust data transmission with error correction and checking capabilities.
DMA for PCI Express (PCIe) Subsystem
The Xilinx® LogiCORE™ DMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the…
ChipScope Pro IBERT for 7 Series GTZ
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTZ transceivers is d…
ChipScope Pro IBERT for 7 Series GTP
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTP transceivers is d…
AXI4-Stream Accelerator Adapter
The AXI4-Stream Accelerator Adapter is a soft Xilinx® LogiCORE™ Intellectual Property (IP) core used as a infrastructure block fo…