Vendor: Xilinx, Inc. Category: Bus Fabric

Memory Interface

Memory Interface is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs.

Overview

Memory Interface is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs. Memory Interface generates unencrypted Verilog or VHDL design files, UCF constraints, simulation files and implementation script files to simplify the design process. Memory Interfaces supported are: DDR3 SDRAM, DDR2 SDRAM, QDRII SRAM, and DDRII SRAM, LP DDR, QDRII+ SRAM, and RLDRAM II.

Key features

  • Memory Interface generates through a Graphic User Interface the unencrypted Verilog or VHDL design files, UCF constraints, and simulation script files to simplify the memory interface design process.
  • Memory modules (DIMM) are supported for DDR3, DDR2 and DDR SDRAMs.
  • OS Support
    • 64-bit/32-bit Linux Red hat Enterprise 4.0
    • 64-bit XP Professional
    • 32-bit Vista business
    • 64-bit SUSE 10
    • Windows XP

Specifications

Identity

Part Number
Memory Interface
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about On-Chip Bus IP cores

What is Memory Interface?

Memory Interface is a Bus Fabric IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Bus Fabric?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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