Learn more about High-Speed IP core
This article describes the various components of noise in a switch-mode DCDC converter and demonstrates how PowerSoCs can minimize those components. The article further shows design examples and demonstrates how PowerSoCs can power high speed IO with performance equivalent to or better than Linear Regulators.
Here's a review of the LTE algorithms and a practical implementation on a Xilinx FPGA. The reference design is tested using multiple video stream with varying encoding rates.
By offloading operations that require high-speed parallel processing onto FPGAs, overall system performance in such wireless operations as FIR filtering, FFTs, digital down and up conversion and FEC blocks can be improved.
The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit.
With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.
Today, High-Speed SerDes serves as the foundation of industry standards such as PCIe, Ethernet, USB, and UCIe, making it a critical technology for modern semiconductor systems. As the industry progresses towards higher data rates and increasingly complex architectures, SerDes continues to play a central role in enabling reliable and scalable connectivity, especially at lower nodes.
