AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
System Controller
Partial Reconfiguration Decoupler IP
The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs.
Overview
The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs. One or more PR Decoupler cores can be used to make the interface between a Reconfigurable Partition (RP) and the static logic safe from unpredictable activity while partial reconfiguration is occurring. When active, user-selected signals crossing between the RP and the static logic are driven to user configurable values. When inactive, signals are passed unaltered. PR Decoupler cores can be connected to the PR Controller IP or custom user controllers to create a complete Partial Reconfiguration management solution.
The PR Decoupler core can be customized for the number of interfaces, type of interfaces, decoupling functionality, status and control. AXI-based interfaces are natively supported; easily and efficiently enable AXI4-Stream based control, AXI4-Stream based status, or AXI4-Lite based status and control.
The PR Decoupler core can be customized for the number of interfaces, type of interfaces, decoupling functionality, status and control. AXI-based interfaces are natively supported; easily and efficiently enable AXI4-Stream based control, AXI4-Stream based status, or AXI4-Lite based status and control.
Key features
- Support for all interface types registered in the Vivado® Design Suite, including customer interfaces
- Multiple interfaces allowed per decoupler
- Unique decoupling behavior per interface
- Each interface can have clock domain crossing support
- Compatible with AXI4-Lite and AXI4-Stream user interfaces
- Multiple status and control options
- Connects directly to the Partial Reconfiguration Controller using the signal based control interface
- Phased decoupling supported
Specifications
Identity
Part Number
Partial Reconfiguration Decoupler IP
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about system controller IP cores
What is Partial Reconfiguration Decoupler IP?
Partial Reconfiguration Decoupler IP is a System Controller IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this System Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this System Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.