Overview
The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs. One or more PR Decoupler cores can be used to make the interface between a Reconfigurable Partition (RP) and the static logic safe from unpredictable activity while partial reconfiguration is occurring. When active, user-selected signals crossing between the RP and the static logic are driven to user configurable values. When inactive, signals are passed unaltered. PR Decoupler cores can be connected to the PR Controller IP or custom user controllers to create a complete Partial Reconfiguration management solution.
The PR Decoupler core can be customized for the number of interfaces, type of interfaces, decoupling functionality, status and control. AXI-based interfaces are natively supported; easily and efficiently enable AXI4-Stream based control, AXI4-Stream based status, or AXI4-Lite based status and control.
Learn more about System Controller IP core
The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit.
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