Vendor: Xilinx, Inc. Category: Ethernet

Hard-Core TEMAC

The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.

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Overview

The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std. 802.3-2002. Differences between that specification and the Xilinx HARD_TEMAC implementation are highlighted and explained in the Specification Exceptions section. The HARD_TEMAC is an intellectual property (IP) soft core designed for implementation in a Virtex-4 FX FPGA.

Key features

  • Filtering of “bad” receive frames to reduce processor bus utilization.
  • Hardware selectable DCR or PLB host interface to configuration registers.
  • GMII and MII interfaces to external PHY devices.
  • SGMII supported through MGT interface to external copper PHY layer.
  • Complies with IEEE 802.3-2000 specification.
  • Full duplex operation.
  • Media Independent Interface Management (MIIM) for access to PHY transceiver registers.

Specifications

Identity

Part Number
Hard-Core TEMAC
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about Ethernet IP cores

What is Hard-Core TEMAC?

Hard-Core TEMAC is a Ethernet IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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