Vendor: Xilinx, Inc. Category: Debug Trace

JTAG to AXI Master

The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals …

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Overview

The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals internal to FPGA in the system. This supports AXI4 interfaces and Lite protocol and can be selected using a parameter. The width of AXI data bus is customizable. This IP can drive AXI4-Lite or AXI4 Memory mapped Slave through an AXI4 interconnect. This can also be connected to interconnect as master. Run time interaction with this core requires the use of the Vivado® logic analyzer feature.

Key features

  • Provides AXI4 master interface
  • Option to set AXI4 and AXI4-Lite interfaces
  • User Selectable AXI datawidth – 32 and 64
  • User Selectable AXI ID width up to four bits
  • Vivado logic analyzer Tcl Console interface to interact with hardware
  • Support  AXI4 and Lite transactions

Specifications

Identity

Part Number
JTAG to AXI Master
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about Debug Trace IP

What is JTAG to AXI Master?

JTAG to AXI Master is a Debug Trace IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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