Vendor: Xilinx, Inc. Category: Video Transport

SMPTE SDI

Supports emerging standards for lowering cost of uncompressed HD video transport Reduce the cost of multichannel SD/HD/3G-SDI des…

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Overview

Supports emerging standards for lowering cost of uncompressed HD video transport

Reduce the cost of multichannel SD/HD/3G-SDI designs through integration of SMPTE compliant SDI interfaces alongside audio/video processing in a Xilinx FPGA.

The Serial Digital Interface (SDI), is widely used in broadcast applications for the transport of uncompressed SD and HD digital video streams over coax cable. The LogiCORE™ IP Triple-Rate SDI interface solution provides receiver and transmitter interfaces for the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards.

Key features

  • SMPTE 259 (SD-SDI)
  • SMPTE 292 (HD-SDI)
  • SMPTE 372 (Dual Link HD-SDI)
  • SMPTE 424 and 425 (3G-SDI) including levels A, B-DL, and B-DS
  • SMPTE 352 (Payload ID)
  • SMPTE RP-165 (SD-SDI EDH)
  • A single reference clock frequency supports reception of five different bit rates:
    • 270 Mb/s SD-SDI
    • 1.485 Gb/s HD-SDI
    • 1.485/1.001 Gb/s HD-SDI
    • 2.97 Gb/s 3G-SDI
    • 2.97/1.001 Gb/s 3G-SDI
  • Automatically detects incoming SDI standard and bit rate
  • Automatically detects video transport format
  • Detects and captures SMPTE 352 packets
  • Checks for CRC errors for HD-SDI and 3G-SDI
  • Optionally checks for EDH errors for SD-SDI
  • Only two reference clock frequencies are required to transmit five different bit rates:
    • 270 Mb/s SD-SDI
    • 1.485 Gb/s HD-SDI
    • 1.485/1.001 Gb/s HD-SDI
    • 2.97 Gb/s 3G-SDI
    • 2.97/1.001 Gb/s 3G-SDI
  • Generates and inserts CRC and line numbers for HD-SDI and 3G-SDI
  • Generates and inserts EDH packets for SD-SDI
  • Generates and inserts SMPTE 352 packets for all SDI standards

Specifications

Identity

Part Number
SMPTE SDI
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is SMPTE SDI?

SMPTE SDI is a Video Transport IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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