Vendor: Xilinx, Inc. Category: Protocol Bridge

AXI4-Stream Accelerator Adapter

The AXI4-Stream Accelerator Adapter is a soft Xilinx® LogiCORE™ Intellectual Property (IP) core used as a infrastructure block fo…

Overview

The AXI4-Stream Accelerator Adapter is a soft Xilinx® LogiCORE™ Intellectual Property (IP) core used as a infrastructure block for connecting hardware accelerators to embedded CPUs.

It provides the AXI4-Stream interface to AXI4 infrastructure components and BRAM/FIFO interface towards Accelerator IP. This IP is used to improve the overall system-level performance for hardware accelerator IP in the FPGA logic.

Key features

  • Connects as a 32-bit slave on AXI4-Lite interface
  • AXI4-Stream data width support of 32, 64, 128, and 256 bits
  • BRAM/FIFO data width support of 8, 16, 32, and 64 bits
  • Supports up to eight channels for Stream-to-Memory (S2M), Memory-to-Stream (M2S), and Memory-to-Memory (M2M)
  • Supports up to four buffers per channel
  • Supports asymmetric Multi-Buffer data width for AXI4-Stream and BRAM/FIFO interface
  • Supports up to eight input scalars, eight output scalars, and eight input scalars for scalar interface

Specifications

Identity

Part Number
AXI4-Stream Accelerator Adapter
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Protocol Bridge IP core

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Frequently asked questions about Protocol Bridge IP cores

What is AXI4-Stream Accelerator Adapter?

AXI4-Stream Accelerator Adapter is a Protocol Bridge IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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