1G/10Gb Ethernet PHY Intel® FPGA IP
Altera
•
HQ:
USA
The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
- Single-Protocol PHY
Compare 18,290 Semiconductor IP Cores from 468 vendors
-
-
Multi-Rate Ethernet PHY FPGA IP
Altera• HQ: USAThe Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
- Single-Protocol PHY
-
Altera• HQ: USA
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
- Single-Protocol PHY
-
Altera• HQ: USA
The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implem…
- Channel Coding
-
Altera• HQ: USA
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Warp Intel® FPGA IP provides a optimized solution fo…
- Video Processing
-
Video and Vision Processing Suite
Altera• HQ: USAThe Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…
- Video Processing
-
Altera• HQ: USA
Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.
- Channel Coding
-
Tone Mapping Operator (TMO) Intel® FPGA IP
Altera• HQ: USAAs a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Tone Mapping Operator (TMO) Intel® FPGA IP corrects …
- Video Processing
-
Reed Solomon II Intel® FPGA IP Core
Altera• HQ: USAThe Reed Solomon II Intel® FPGA intellectual property (IP) core offers a fully parameterizable Reed Solomon encoder and decoder.
- Channel Coding
-
Altera• HQ: USA
The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder.
- Channel Coding
-
Altera• HQ: USA
A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…
- Control Logic
-
High-Speed Reed Solomon Intel® FPGA IP Core
Altera• HQ: USAThe High-Speed Reed Solomon Intel® FPGA intellectual property (IP) core uses a large parallel architecture to achieve a large thr…
- Channel Coding
-
Altera• HQ: USA
The FIR II Intel IP core provides a fully-integrated finite impulse response (FIR) filter function optimized for use with Intel F…
- Filters Transforms
-
Altera• HQ: USA
The Fast Fourier transform (FFT) Intel FPGA intellectual property (IP) core is a high-performance, parameterizable FFT processor.
- Filters Transforms
-
Altera• HQ: USA
The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon…
- Filters Transforms
-
Altera• HQ: USA
The Bose, Chaudhuri, and Hocquenghem (BCH) error correction intellectual property (IP) core is typically used in NAND flash appli…
- Channel Coding
-
Altera• HQ: USA
The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with t…
- Channel Coding
-
Altera• HQ: USA
Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy…
- Channel Coding
-
Siemens EDA* AXI Verification IP Suite
Altera• HQ: USAThe Siemens EDA AXI Verification IP Suite (Intel® FPGA Edition) provides bus functional models (BFMs) to simulate the behavior an…
- Verification IP
-
Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
PQShield• HQ: United KingdomPQCryptoLib-Embedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
- Post Quantum