Vendor: ASICFPGA Category: Video Processing

Deep-learning noise reduction IP core

Deep-learning spatial noise reduction + temporal noise reduction

Overview

Noise reduction is a key issue in any camera system to improve the visual appearance of the images. As the light level decreases, the sensor gain goes up and the noise level increases. AI 2D+3DNR is a deep-learning noise reduction IP core for very low light conditions, offered as a separate IP. It removes both spatial and temporal noise, including color noise and luminance noise, and keeps edges and fine texture. The deep-learning motion compensation aligns the previous frame with the current frame before temporal filtering, so moving objects keep their detail and ghost images are reduced. The strength follows the sensor gain, so the core works from normal light to very low light without manual tuning.

Key features

  • Deep-learning spatial noise reduction + temporal noise reduction
  • Deep-learning motion compensation for temporal filtering (fewer ghost images)
  • Noise reduction strength set automatically by the sensor gain
  • Bayer domain processing
  • Verified at 1920x1080 30 fps on AMD Kria KV260 (Zynq UltraScale+ MPSoC) with Sony IMX678
  • Needs external DDR SDRAM for frame buffers

Specifications

Identity

Part Number
AI 2D+3DNR
Vendor
ASICFPGA
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Canada

Learn more about Video Processing IP core

Frequently asked questions about Video Processing IP

What is Deep-learning noise reduction IP core?

Deep-learning noise reduction IP core is a Video Processing IP core from ASICFPGA listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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