Customizable Video Input controller
CVI is a fully Customizable Video Input controller IP core.
- Video Processing
- silicon proven
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Customizable Video Input controller
CVI is a fully Customizable Video Input controller IP core.
5GHz Multiplying PLL on TSMC 28nm
Analog-PLL For Frequency Multiplying on TSMC 28nm HPM/HPC
Compact LossLess Encoder RTL Core
Extremely high throughput contributes to realization of the complete lossless compression and decompression.
1:2 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
Silicon agnostic implementation of the structure agnostic mapping method described in the IEEE 1914.3 standard The Radio Over Eth…
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver
The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
1.7GHz Multiplying PLL on TSMC 28nm
Analog-PLL For Frequency Multiplying on TSMC 28nm HPM/HPC
Silicon Proven 1G Ethernet PHY IP as Whitebox
1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…
Graphics Processor Overlay IP Core
The GPU_OVERLAY IP Core is a versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text…
MIPI D-PHY Transmitter/Receiver for TSMC 22nm ULL
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 22nm ULL process.
MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI
The MIPI® D-PHY Transmitter/Receiver is useful 4 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of Samsung 28nm FD-SOI process.
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 40nm LP process.
Tensilica AI Max - NNA 110 Single Core
Single-core neural network accelerator offering from 0.5 to 4 TOPS Optimized for machine learning inference applications The Cade…
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP).
128X8 Bits OTP (One-Time Programmable) IP, CanSemi 0.18um 1.8V/3.3V Process
The ATO00128X8CA180L333NA is organized as a 128-bit by 8 one-time programmable (OTP).This is a kind of non-volatile memory fabric…
TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple …
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.
The Rambus HBM3E / HBM3 controller cores are designed for use in applications requiring high memory bandwidth and low latency inc…