What is Customizable Video Input controller?
Customizable Video Input controller is a Video Processing IP core from TES Electronic Solutions listed on Semi IP Hub.
CVI is a fully Customizable Video Input controller IP core.
CVI is a fully Customizable Video Input controller IP core. The video input controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.
The main functionality of CVI is reading an ITU-656 video input stream typically coming from a physical video input interface, e.g. a LVDS PHY or a video ADC, and writing the video data in RGB format to memory via DMA. Several on-the-fly operations on the video data can be applied such as clipping, scaling, color conversion, gamma correction, dithering and de-interlacing.
On the input side CVI can accept RGB as well as YCBCR color formats, in the latter case applying the on-the-fly conversion YCBCR to RGB.
CVI Customizability
Based on a highly modular architecture the CVI offers a wide range of features. The target set of features is configurable at synthesis time, allowing an optimal tailored solution for the target application: not needed features and the related modules are not synthesized, resulting in less resource usage (FPGA logic elements or ASIC gates) and power consumption.
The selected (configured) features can be controlled at run-time via software-programmable registers. To ease the application programmers’ life an ANSI-C software driver is delivered providing a set of comfort functions.
Note: some files may require an NDA depending on provider policy.
Customizable Video Input controller is a Video Processing IP core from TES Electronic Solutions listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.