Gen-Z Physical Layer for PCIe IP Core
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe …
- Single-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Gen-Z Physical Layer for PCIe IP Core
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe …
Gen-Z Physical Layer for 802.3 IP Core
The IntelliProp IPC-GZ196A-ZM Gen-Z Physical Layer for 802.3 is an IP Core that allows companies to attach a Gen-Z core to an 802…
The IntelliProp IPC-GZ190A-HI Gen-Z Requester is an IP Core that allows companies to build Gen-Z compliant Requester devices.
The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices.
The K-best decoder is part of the MIMO decoder.
General Purpose Input/Output Controller
The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller.
General Purpose Input/Output Controller
The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
High speed analog circuits for USB3.0 PHY application 745um*620um
The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller.
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller.
The CC-TIMER-APB is a synthesisable Verilog model timer counter controller.
Peripheral Direct Memory Access Controller
The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller.
UART Serial Interface Controller
The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller.
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller.
I2C Master Serial Interface Controller
The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller.
The LTE Lite PHY supplied as a portable and synthesizable Verilog-2001 IP.
Embedded OTP (One-Time Programmable) IP, 768x10 bits for 3.3V Green
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 512x38 bits for 1.5V/5V BCD
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…
Embedded OTP (One-Time Programmable) IP, 512x32 bits for 1.5V/5V LP
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…