Learn more about Edge AI Accelerator IP core
While lightweight architectures like MobileNetV2 employ Depthwise Separable Convolutions (DSC) to reduce computational complexity, their multi-stage design introduces a critical performance bottleneck inherent to layer-by-layer execution: the high energy and latency cost of transferring intermediate feature maps to either large on-chip buffers or off-chip DRAM. To address this memory wall, this paper introduces a novel hardware accelerator architecture that utilizes a fused pixel-wise dataflow.
In this work, the authors present a domain-specific RISC-V microprocessor architecture and design flow tailored for TM inference. Leveraging the modular structure of RISC-V, we design a reduced instruction subset processor that retains programmability while targeting improved performance and lower energy consumption for TM workloads.
A look at Kinara’s accelerator and NXP processors which combine to deliver edge AI performance capable of delivering smart camera designs
In an ever-changing technology landscape, USB (Universal Serial Bus) has been a cornerstone since its inception in the mid-1990s. Initially designed to simplify the connection of peripherals to personal computers, USB has undergone significant transformations to meet the growing demands for faster data transfer rates, improved power delivery, and enhanced versatility.
Enter the Multi-Protocol SerDes (Serializer/Deserializer)—a flexible, reusable IP block that allows a single PHY to support multiple serial communication protocols, such as PCIe, SATA, Ethernet, USB, and more. This approach enables SoC vendors to meet diverse customer requirements and application needs without redesigning I/O for each target market.
Kurt Shuler, Arteris
