Overview
The H.264 Decoder IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The H.264 Decoder IP can be implemented in any technology. The H.264 Decoder core supports the ISO/IEC 14496-10/ITU-T H.264 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. The H.264 Decoder IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The H.264 Decoder IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.
Learn more about Video Processing IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
