Vendor: Certus Semiconductor Category: Analog

55nm Specialized Analog I/O Library

Specialized Analog I/O Library with 1.2V, 1.8V, 3.3V, and 5V integrated Analog I/Os and ESD; includes a custom 12V I/O ESD soluti…

GlobalFoundries 55nm LPx View all specifications

Overview

Specialized Analog I/O Library with 1.2V, 1.8V, 3.3V, and 5V integrated Analog I/Os and ESD; includes a custom 12V I/O ESD solution.

Key features

  • Core Device: 2.5V Standard with 1.8V UD and 3.3V OD Devices
  • I/O Device: 1.8V
  • BEOL: 7 metals + RDL, 5 normal, 2 think (EA, EB), top LB
  • PAD: Flipchip, 60um pitch
  • Cell heights: 80um
  • VDD Core: N/A
  • AVDD: 1.8V ± 10% (3 types of Analog voltage and I/Os are supplied)
    • 3.3V ± 10%
    • 0-12V MAX
  • Temperature: -40C to 125C
  • ESD: 2kV HBM, 500V CDM, Latch-up Immune

What’s Included?

  • GDSII layouts
  • OA Database for LVS and Simulation
  • Spectre Netlist
  • Cadence Netlist

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 55nm LPx —

Specifications

Identity

Part Number
GlobalFoundries 55nm LPx - BCD I/O Library
Vendor
Certus Semiconductor
Type
Silicon IP

Provider

HQ: United States

Learn more about Analog IP core

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This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.

Field Induced CDM Explained

Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.

One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

Frequently asked questions about Analog I/O Pad Library IP cores

What is 55nm Specialized Analog I/O Library?

55nm Specialized Analog I/O Library is a Analog IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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