Vendor: CloudBEAR, LLC Category: CPU

32-bit RISC-V compact high-performance embedded core

32-bit RISC-V compact high-performance embedded core.

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RISC-V View all specifications

Overview

32-bit RISC-V compact high-performance embedded core.
Ideal for control/compute/acceleration workloads requiring high performance in power constrained environment.

Key features

  • Configurable instruction set architecture:
    • 32-bit RISC-V with 32 integer registers (I extension)
    • Integer multiplication and division (M extension)
    • Atomic operation support (A extension)
    • Compressed mode for better code density (C extension)
    • IEEE 754-2008 compliant single precision floating point (F extension)
    • IEEE 754-2008 compliant double precision floating point (D extension)
    • User mode interrupt handlers (N extension)
    • Bit manipulation instructions support (B extension)
    • Scalar cryptography instructions support (K extension)
    • Digital signal processing instructions support (P extension)
  • Dual instruction issue
  • Machine and User modes
  • 9 stage in-order pipeline
  • Advanced branch predictor: BTB, BHT, RAS
  • Configurable memory subsystem: L1 I/D-caches, TCMs
  • Front-port to access TCMs by external masters
  • Configurable interrupt subsystem
    • Platform Level Interrupt Controller (PLIC)
    • Core Local Interruptor (CLINT): timer + software interrupts
    • Local interrupt support to provide fast handling
    • Core Local Interrupt Controller (CLIC)
    • Non-Maskable Interrupts (NMIs)
  • ECC memory protection (SEC-DED)
  • Physical memory protection
  • Integrated debug controller including HW breakpoints
  • System bus access
  • Compact JTAG support
  • Trace support
  • Power management support
  • AXI/AHB configurable interfaces
  • Performance
    • 2.47 DMIPS/MHz
    • 4.6 CoreMark/MHz
  • Frequency
    • 1.2 GHz (TSMC, 28nm HPC+, SSG corner)

Block Diagram

BR-351 block diagram

Benefits

  • Memory subsystem
    • Support of configurable TCMs address ranges. TCM arbiter allows TCMs be accessible by fetch, load/store and via front-port. Optional instruction/data caches may be used with the following features:
      • N-way set associative
      • Configurable cache line
      • Prefetcher
      • Priority chunk support
    • Power management
      • Core completes all activity including cache requests and enter WFI mode. Support of external power management unit to provide clock gating and memory sleep
    • Security
      • Physical memory protection (PMP) is key mechanism to provide isolation between different software components and limit their access to hardware. Up to 16 PMP regions are supported in BR-351.
    • Multi-core support
      • Preintegrated and tested subsystem is available. Flexible bus infrastructure to connect the cores itself and external world is supported. Different inter core communication mechanisms are possible:
        • Software interrupts in CLINT
        • Atomic in neighbor core TCMs
      • Development Tools
        • Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
      • 3rd Party Development Tools
        • IAR Embedded Workbench®
        • SEGGER Embedded Studio for RISC-V
        • TRACE32® debugger for RISC-V
      • Compatible Debug Probes
        • BR-351 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
          • Digilent HS2
          • Digilent HS3
          • Olimex ARM-USB-TINY
          • Olimex ARM-USB-TINY-H
          • Olimex ARM-USB-OCD
          • Olimex ARM-USB-OCD-H
          • IAR I-jet
          • SEGGER J-Link
          • TRACE32® debugger for RISC-V

Specifications

Identity

Part Number
BR-351
Vendor
CloudBEAR, LLC
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

CloudBEAR, LLC
HQ: Russia
Contact CloudBEAR, LLC

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Frequently asked questions about CPU IP cores

What is 32-bit RISC-V compact high-performance embedded core?

32-bit RISC-V compact high-performance embedded core is a CPU IP core from CloudBEAR, LLC listed on Semi IP Hub.

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