Clock Buffer - X-FAB XT018-0.18µm BCD-on-SOI CMOS
The TS_CLKBUF_25pF_X8 transfers input clock signal to other digital or mixed-signal chips, which feature altogether a maximum loa…
100MHz single-ended to differential clock buffer for UMC 40nm LP.
100MHz single-ended to differential clock buffer for UMC 40nm LP.
IP
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O (05) Library
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (05) Library developed by VeriSilicon is optimized for Grace Semiconductor Ma…
8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
The TS_XOSC_40M_X8 is a 8MHz / 40MHz Pierce oscillator that generates a VCC-level logic square wave when a 8MHz / 40MHz quartz cr…
GNSS (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) Ultra-low power RF Receiver IP
This GNSS RF Receiver IP is silicon-proven in TSMC40nm ULP process node, offers comprehensive support for all current satellite-b…
LIN Bus Master/Slave Controller
The LIN-CTRL core is a communication controller that transmits and receives LIN frames to perform serial communication according …
The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors,…
The Janus Network on Chip (NoC) is a new configurable soft IP designed to speed up the system-on-chip (SoC) and full system desig…
Digital Video Anti-aliasing filter IP Core
The ALIAS_FILTER IP Core is a fully pipelined anti-aliasing filter for use in digital video applications.
Host / device LIN controller IP
The LIN Controllers IP– Local Interconnect Network Controllers IPs are compliant to LIN 2.0, 2.1 & 2.2A Specifications.
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
Intelligent Sensor and Power Management Design Platform
The IQonIC Works ISP is an integrated ASIC design platform for low power analog/mixed signal ASICs for IoT, Smart Home, Healthcar…
BAYER_TO_RGB is a fully pipelined Bayer-mapped to RGB converter IP Core.
LogiCORE IP Serial RapidIO Gen 2
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a flexible and o…
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process
In production since 2012 for dozens of designs.The Cadence® Memory Model Verification IP (VIP) for Flash Octal SPI (OSPI) Flash p…