Digital Video Anti-aliasing filter IP Core

The ALIAS_FILTER IP Core is a fully pipelined anti-aliasing filter for use in digital video applications. The design implements a low pass filter response on the source video in order to alleviate problems such as jagged edges, stepped lines and Moiré interference patterns. This is especially important when downscaling and upscaling video by large factors.

Internally, the circuit uses a 3x3 pixel filter kernel with 5 different possible filter settings. The input and output pixels are 24-bit in RGB 8:8:8 format. The image size is fully programmable with support for up to 216 x 216 pixels.

Pixels flow into the IP Core in accordance with the valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when pixin_val and pixin_rdy are both high. Likewise, at the output interface, pixels and syncs are sampled on a the rising edge of clk when pixout_val and pixout_rdy are both high.

• Technology independent soft IP Core for FPGA, ASIC and SoC devices
• Supplied as human-readable VHDL (or Verilog) source code
• Fully pipelined architecture with simple flow control and AXI4 compatible data streaming interfaces
• Supports all image resolutions up to 216 x 216 pixels
• Support for 5 different low-pass filter responses including, box blur, low-cost smoothing, Gaussian and custom kernels
• Features a 3 x 3 image filter
• Input / output rate of 1 x 24-bit pixel per clock
• No frame buffer required
• Small implementation size
• Support for 300 MHz+ operation on basic FPGA and SoC devices

• Low-pass filtering of digital video to remove high frequency artefacts such as jagged edges, stepped lines and Moiré interference patterns
• Optimization of video from image sensors and cameras
• Forms an essential stage when downscaling and upscaling by large factors. For instance, 4K video to HD or SD and vice versa