How to tackle serial backplane challenges with high-performance FPGA designs
Flexible FPGA fabric, embedded multi-gigabit transceivers, and off-the-shelf IP enable robust, high performance, and high-integration serial backplane interface solutions
Vendor:
Xilinx, Inc.
Category:
RapidIO
LogiCORE IP Serial RapidIO Gen 2
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a flexible and o…
Overview
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer core. This IP solution is provided in netlist form with supporting example design code. The Gen 2 IP supports 1x, 2x, and 4x lane widths. It comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design, which allows complete flexibility in selection functional blocks needed for a given application. This solution supports Verilog design environment. This IP core utilizes AXI-4 Streaming interface for data path and AXI-4 Lite interface for configuration (maintenance) transactions. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.
For Serial RapidIO Gen 1.3 (with extensions for Gen 2 5G line rates) Xilinx LogiCORE IP, please visit Serial RapidIO LogiCORE IP
For Serial RapidIO Gen 1.3 (with extensions for Gen 2 5G line rates) Xilinx LogiCORE IP, please visit Serial RapidIO LogiCORE IP
Key features
- 1x, 2x, & 4x Serial PHY - supports Artix-7, Kintex-7, Zynq-7000, Virtex-7, and Virtex-6 FPGAs
- 1x, 2x & 4x Serial PHY - supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gbps line speed
- Supports IDLE1 and IDLE2 sequence
- Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
- Support for 8/16 bit device IDs, programmable source ID on all outgoing packets
- Support for priority based re-transmit suppression
- Independently configurable 8/16/32 packet deep TX and RX buffer depths
- AXI4-Stream interface for Data path and AXI4-Lite for the configuration Interface
Specifications
Identity
Part Number
EF-DI-RIO-SITE
Vendor
Xilinx, Inc.
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about RapidIO IP cores
What is LogiCORE IP Serial RapidIO Gen 2?
LogiCORE IP Serial RapidIO Gen 2 is a RapidIO IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this RapidIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RapidIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.