1.2V SLVS Transceiver in UMC 110nm
A 200Mbps 1.2V SLVS transceiver solution.
- UMC
- 110nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1.2V SLVS Transceiver in UMC 110nm
A 200Mbps 1.2V SLVS transceiver solution.
The GR2000 BLE Platform IPs are wireless IP targeting Bluetooth Low Energy applications.
This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solut…
VID_OVERLAY is a versatile video multiplexer that allows one video stream to be inserted over another.
Digital Video Anti-aliasing filter IP Core
The ALIAS_FILTER IP Core is a fully pipelined anti-aliasing filter for use in digital video applications.
Verification IP for Ultra Ethernet (UEC)
The Verification IP for Ultra Ethernet (UEC) provides a comprehensive set of protocol, methodology, verification and productivity…
High-scalable, high-performance Interconnect fabric IP with cache coherence support
StarNoC-700 is the vendor's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, ena…
Interconnect fabric IP with cache coherence support
StarNoC-500 is the vendor's first self-developed interconnect fabric IP with cache coherence support, supporting the construction…
Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz…
64-bit application processor for energy-efficient computation
Dubhe-80 processor features a 9+ stage, 3-issue, out-of-order pipeline, fully compliant with a rich set of RISC-V extensions of R…
CPU IP Following the RVA23 Profile, supporting RVV1.0 and all extensions of Vector Crypto
Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH,…
High Performance 64-bit RISC-V Processor
Dubhe-90 is a high-performance commercial RISC-V CPU Core IP that is deliverable.
Embedded USB2 (eUSB) Controller + PHY IP
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1…
Ultra-low power high dynamic range image sensor
Based on a time-domain pixel-level A/D conversion, its patented pixel architecture enables the capture of high dynamic range imag…
3.3V Capable GPIO on TSMC 28nm RF HPC+
The 3.3V capable GPIO is an IP macro for on-chip integration.
1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
The 1.2V Thin Gate GPIO is an IP macro for on-chip integration.
Ethernet Switch Advanced L2/VLAN 48x1G + 5x10G
This L2 Ethernet Switch IP Core offers a full range of features with full wirespeed on all ports plus a high speed CPU port.
Supports DMA transfers between M_CAN Message RAM and System Memory Up to sixteen 32-bit timestamps supported by TSU On reception …
Smart connectivity for mobile, IoT, and automotive innovation The DI3CS device is an I3C Target that complies with the MIPI® Alli…
GPNPU Processor IP - 32 to 864TOPs
Designed from the ground up to address significant machine learning (ML) inference deployment challenges facing system on chip (S…