Ethernet Switch Advanced L2/VLAN 48x1G + 5x10G

This L2 Ethernet Switch IP Core offers a full range of features with full wirespeed on all ports plus a high speed CPU port.

The IP is compatible with ASIC technology as well as FPGA technology from most vendors.

Each port has priority queues which are controlled by a strict priority scheduler allowing the most timing critical packets to get minimal delay while providing a fairness between queues.

The switching core is built around a shared buffer memory architecture allowing head-of-line-blocking-free switching on all ports operating at wire-speed. It offers dynamic per port and per priority usage of the packet buffer memory along with buffer limiters to limit how much an egress port / priority uses of total buffer memory.

The switching core also features multiple VLAN tagging and un-tagging along with egress VLAN translation.

The L2 Ethernet Switching IP features a processor interface allowing setup of tables and register. It also features a packet based CPU port which can be used to both send and receive ethernet frames to/from the switching IP.

This IP requires no software setup to be used, it is ready to receive and forward Ethernet frames once downloaded to FPGA and connected to MACs. It has hardware learning for MAC addresses.

• 48 ports of 1 Gigabit Ethernet.
•  5 ports of 10 Gigabit Ethernet.
•  Full wire-speed on all ports and all Ethernet frame sizes.
•  Store and forward shared memory architecture.
•  Support for jumbo packets up to 16359 bytes.
•  Passes maximum overlap mesh test (RFC2899) excluding the CPU port, for all packet sizes up to 1601 bytes.
•  Input and output mirroring.
•  RSPAN - Remote Switch Port Analyzer
•  8 source MAC address ranges with a number of different actions.
•  8 destination MAC address ranges with a number of different actions.
•  32,768 entry L2 MAC table, hash based 8-way.
•  4,096 entry VLAN table.
•  64 entry synthesized CAM to solve hash collisions.
•  8 entries of the synthesized CAM are fully maskable.
•  1,024 entry L2 multicast table.
•  Automatic aging and wire-speed learning of L2 addresses. Does not require any CPU/software intervention.
•  Spanning tree support, ingress and egress checks.
•  64 multiple spanning trees, ingress and egress checks.
•  Egress VLAN translation table allowing unique VID-to-VID translation per egress port.
•  VLAN priority tag can bypass VLAN processing and be popped on egress.
•  Support for masking all look-up keys for L2 MAC table.
•  4432 entries of ingress classification / ACL Lookups. The classification / ACL keys are configurable for each source port and the fields are selected from a incoming packets L2, L3 or L4 fields. The selection is described in 11.2 The classificaiton / ACL key can be up to 322 bits long. The classification / ACL lookup is based on a combination of hash and TCAM. The actions which can be done is listed below:
  •  Multiple actions can be assigned to each result. All results can be done in parallel if the user so wishes.
  •  Result action can be to drop a packet.
  •  Result action can be to send a packet to the CPU port.
  •  Result action can be to send a packet to a specific port.
  •  Result action can be to update a counter. There are 256 counters which can be used by the classification / ACL engine.
  •  Result action can be to force packet to a specific queue on a egress port.
  •  Result action can be to assign a meter/market/policer to measure the packet bandwidth.
  •  Result action can be to assign a color to the packet which is used by the meter/marker/policer.
  •  Result action can be to force the packet to use a specific VID when doing the VLAN table lookup.
  •  Result action can be to do a input mirror on a packet.
  •  Result action can be to not allow the packet to be learned in L2 MAC table.
•  The ingress configurable classification / ACL engine can use the type and code fields from ICMP frames.
•  The ingress configurable classification / ACL engine can use the fields, including the group address, from IGMP frames.
•  17236480 bits shared packet buffer memory for all ports divided into 13466 cells each of 160 bytes size
•  8 priority queues per egress port.
•  Configurable mapping of egress queue from IP TOS, MPLS exp/tc or VLAN PCP bits.
•  128 ingress admission control entries.
•  Deficit Weighted Round Robin Scheduler.
•  Bandwidth shapers per port.
•  Individual bandwidth shapers for each priority on each port.
•  Individual bandwidth shapers for each queue on each port.
•  Egress queue resource limiter with 27 sets of configurations.
•  Configuration interface for accessing configuration and status registers/tables.
•  Multicast/Broadcast storm control with separate token buckets for flooding, broadcast and multicast packets.
•  Multicast/Broadcast storm control is either packet or byte-based, configurable per egress port.
•  LLDP frames can optionally be sent to the CPU.
•  Attack prevention by TCP flag rules combined with TCP-port and IP address checks, this also includes IMCP length attack checks.
•  IEEE 1588 / PTP support for 1-step and 2-step Ordinary Clock mode. The switch supports transfer of 8 byte timestamp from receive MAC to software and form software to transmit MAC.
•  Queue management operations:
  •  Disable scheduling of packets on a port.
  •  Disable queuing new packets to a port.
  •  Allow a port to be drained without sending out packets.
  •  Allow checking if a port is empty or not.

•  Unencrypted Verilog source code of IP.
•  Datasheet of registers & theory of operations.
•  C source code for accessing registers.
•  Easy to parse YML file for register mapping.
•  Verilog testbench.
•  Low-level device driver.