Vendor: Sofics Category: GPIO

1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+

The 1.2V Thin Gate GPIO is an IP macro for on-chip integration.

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Overview

The 1.2V Thin Gate GPIO is an IP macro for on-chip integration. It is a 1.2V general purpose I/O that does not rely on thick-gate devices. Only thin-gate, 0.9V capable core MOS devices are used in the design.

Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. Extra features such as programmable hysteresis can be supported upon request.

The 1.2V Thin Gate GPIO targets radiation hard applications or other applications prohibiting the use of thick gate I/O devices. By default, a 2kV HBM ESD protection is included. This is however easily scaled to any desired level. This specific IP macro is designed in TSMC 28nm RF HPC+, and can be ported to other technologies upon request using Sofics inhouse design tool flow.

Physical implementation 

  • TSMC 28nm RF HPC+ 1P9M 
  • No thick gate devices, MIM cap or STI required 
  • Pad size 70um x 70um

Key features

  • Overvoltage tolerant design 
  • Core domain isolation 
  • Compatible with TSMC I/O ring 
  • Vertical and horizontal orientation 
  • Temp range -40°C to 125°C TJ 
  • 100kΩ pullup/pulldown 
  • Integrated 2kV HBM ESD 
  • Programmable slope control 
  • 0.9V digital interface 
  • Bias generation circuit can be shared over multiple I/O instances

Block Diagram

1.2V Capable GPIO on TSMC 28nm RF HPC+ block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm —

Specifications

Identity

Part Number
1.2V Capable GPIO on TSMC 28nm RF HPC+
Vendor
Sofics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Sofics
HQ: Belgium
Contact Sofics

Learn more about GPIO IP core

GPIO Solutions for CERN’s Radiation-Hardened Applications

For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.

Ensuring reliability in Advanced IC design

To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.

Not all overvoltage tolerant GPIOs are the same

Most foundries provide GPIO libraries to their fabless customers. These libraries contain different elements like supply/ground pads, analog I/Os, digital I/Os, corner cells, filler cells, power-on-reset circuits. Frequently the foundry includes cells for different voltage domains. In 40nm CMOS the IC designer can use cells for 1.8V, 2.5V and 3.3V for instance.

Frequently asked questions about GPIO Pad Library IP cores

What is 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+?

1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+ is a GPIO IP core from Sofics listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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