Vendor: StarFive Category: Coherency

Interconnect fabric IP with cache coherence support

StarNoC-500 is the vendor's first self-developed interconnect fabric IP with cache coherence support, supporting the construction…

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Overview

StarNoC-500 is the vendor's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC.

Key features

Providing NoC with cache coherence:

  • connecting multiple CPU clusters, IO devices, and DDR, and maintaining cache coherence within the SoC.

High Performance

  • Provides Last Level Cache (LLC), offers Snoop Filter, improves the efficiency of coherence maintenance modules, and memory hierarchy performance.

Efficient Data Exchange

  • Supports CPU and IO device sharing of LLC, simplifying CPU and IO data exchange and improving performance.

Low Power Consumption

  • Supports LLC way shutdown, cache retention, and other low-power technologies.

High Reliability

  • Snoop Filter and LLC support SEC-DED (Single Error Correction Double Error Detection).

Control Interface Support (CFG & MMIO):

  • CPU configuration of IO devices and on-chip SRAM reading; IO device access and configuration of on-chip interconnect coherence.

Block Diagram

StarNoC-500 block diagram

Benefits

  • Support multiple Fully Coherent Master (FCM)ports
  • Support multiple CPU core/cluster configuration
  • Support Component Aggregation Layer (CAL)
  • Support multiple Coherent IO (CIO) ports
  • Frequency: 1.2 Ghz@12nm (Reference)
  • Cache Size: Typical 4 MB (Configurable)
  • Bus Width: 256 Bit (Configurable)
  • High bandwidth, low power consumption, low latency

Specifications

Identity

Part Number
StarNoC-500
Vendor
StarFive
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

StarFive
HQ: China
Contact StarFive

Learn more about Coherency IP core

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.

Frequently asked questions about Coherency Interconnect IP cores

What is Interconnect fabric IP with cache coherence support?

Interconnect fabric IP with cache coherence support is a Coherency IP core from StarFive listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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