Vendor: StarFive Category: Coherency

High-scalable, high-performance Interconnect fabric IP with cache coherence support

StarNoC-700 is the vendor's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, ena…

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Overview

StarNoC-700 is the vendor's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, enabling the construction of manycore SoC solution.

Key features

Providing NoC with cache coherence

  • Connecting up to 256 CPU cores, IO devices, and DDR, while maintaining cache coherence within the SoC scope

High Performance:

  • Providing a maximum of 512 MB Last Level Cache (LLC) with Snoop Filter, enhancing the efficiency of coherence maintenance modules and memory hierarchy performance.

High scalability

  • Employing mesh NoC to enhance expandability, and a dedicated control NoC to support control command transmission

Low latency

  • Adopting a semi-custom design approach to reduce NoC transmission latency.

Efficient data exchange

  • Supporting CPU and IO devices to share the LLC, simplifying CPU and IO data exchange, and improving performance

Low power consumption

  • Supporting low power consumption technologies such as LLC way shutdown and Architecture Clock Gating

High reliability

  • Snoop Filter and LLC support ECC (SEC-DED, Single Error Correction Double Error Detection)

Block Diagram

StarNoC-700 block diagram

Benefits

  • High bandwidth, low power consumption, low latency
  • Support Component Aggregation Layer (CAL)
  • Topology: Mesh
  • Support multiple I/O Coherent Master Nodes (CIO)
  • Maximum node count: 12x12
  • Single node supports 3-5 devices
  • Configurable data path link width: 128/256/512b

Specifications

Identity

Part Number
StarNoC-700
Vendor
StarFive
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

StarFive
HQ: China
Contact StarFive

Learn more about Coherency IP core

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.

Frequently asked questions about Coherency Interconnect IP cores

What is High-scalable, high-performance Interconnect fabric IP with cache coherence support?

High-scalable, high-performance Interconnect fabric IP with cache coherence support is a Coherency IP core from StarFive listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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