Vendor: Xilinx, Inc. Category: Network-On-Chip

AXI SmartConnect

The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…

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Overview

The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado® IP Integrator block design in the Vivado Design Suite.

AXI SmartConnect is a drop-in replacement for the AXI Interconnect v2 core. AXI SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention.

Key features

  • Up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI) per instance
  • Instances of SmartConnect can be cascaded to interconnect a larger number of masters/slaves or for organizing the interconnect topology
  • AXI Protocol compliant
  • Burst transactions are automatically split, as needed, to remain AXI compliant
  • Interface Data Widths (bits):
    • AXI4 and AXI3: 32,64,128,256,512 or 1024
    • AXI4-Lite: 32 or 64-bit
  • Transactions between interfaces of different data widths are automatically converted by AXI SmartConnect

Specifications

Identity

Part Number
AXI SmartConnect
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about NoC IP cores

What is AXI SmartConnect?

AXI SmartConnect is a Network-On-Chip IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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