Vendor: Xilinx, Inc. Category: Test / Debug

ChipScope Pro (IBERT) for Virtex-6 FPGA GTH

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…

Overview

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable core that can be used to evaluate and monitor Virtex-6 GTH transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the serial transceivers. Communication logic is also included, to allow the design to be run-time accessible through JTAG. The IBERT core is a self-contained design, and when it is generated, will run through the entire implementation flow, including bitstream generation.

Key features

  • Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core.
  • Has user-selectable number of Virtex-6 FPGA GTH Transceivers.
  • Each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width.
  • Requires a system clock sourced from a pin.

Specifications

Identity

Part Number
ChipScope Pro (IBERT) for Virtex-6 FPGA GTH
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about SerDes Test / Debug IP cores

What is ChipScope Pro (IBERT) for Virtex-6 FPGA GTH?

ChipScope Pro (IBERT) for Virtex-6 FPGA GTH is a Test / Debug IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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