Audio I2S
The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to…
Overview
The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to implement Inter-IC-Sound (I2S) interface used to connect audio devices for transmitting and receiving PCM audio.
Key features
- AXI4S Compliant
- Can be configured up to 4 I2S interfaces, each channel supporting 2 audio channels
- Can be configured up to 4 stereo or 8 independent channels
- 16/24 bit data support
- Master I2S mode
- Configurable FIFO depth
- AES Channel Status Extraction/Insertion
- License free IPs
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about I2S IP core
FPGAs - The Logical Solution to the Microcontroller Shortage
Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time
Enabling AI Vision at the Edge
CSoC Platform / Digital Subsystem IP for IoT
Growing audio requirements in SoCs
Frequently asked questions about I2S IP cores
What is Audio I2S?
Audio I2S is a I2S IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this I2S?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2S IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.