Xilinx HMC Controller
The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect …
Overview
The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect with external HMC (Hybrid Memory Cube) devices. The core provides either Xilinx HMC Transaction Layer or AXI4-MM interface
Key features
- Fully compliant with Hybrid Memory Cube Specification Revision 1.x
- Support 10 Gb/s, 12.5 Gb/s, 15 Gb/s SerDes I/O interface
- Support either GTH or GTY transceiver use
- Support both HMC link modes
- Half-width link (8-lane) supported
- Full-width link (16-lane) supported
- Up to 240 Gb/s full-duplex bandwidth
- Two interface modes
- HMC core mode provides Xilinx HMC Transaction Layer with host controller only instantiation. Allows you todevelop your user layer to interface between the user logic and controller IP
- HMC user mode provides standard AXI4-MM interface with Xilinx HMC user layer logic
- AXI4-Lite slave interface for configuration access
- Configurable internal bus width (2~12 flit)
- Support dynamic lane detection and reversal
- Support user defined lane-to-lane mappings
- Support dynamic lane polarity inversion
- Optional user ID reorder logic
- Optional data channel alignment bypass for area optimization
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about HMC Interface IP
What is Xilinx HMC Controller?
Xilinx HMC Controller is a HMC IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this HMC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HMC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.