T2M GmbH IP Cores

The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.

• Single-Protocol PHY
• In Production
• Immediate

The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• Single-Protocol PHY
• In Production
• Immediate

Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate.

• V-By-One
• In Production
• Immediate

The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices.

• V-By-One
• In Production
• Immediate

V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment c…

• V-By-One
• In Production
• Immediate

The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…

• TSMC
• 55nm
• GP
• In Production

The GPHY is a integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption.

• Single-Protocol PHY
• In Production
• Immediate

low-cost stereo digital to analog converter for audio applications.

• 24 Bit
• TSMC
• 28nm
• Silicon Proven

This is a low-cost stereo analog to digital converter for digital audio applications.

• 18 Bit
• TSMC
• 28nm
• HPC
• Silicon Proven

Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.

• SMIC
• 40nm
• LP
• In Production

A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data …

• USB 3.1

Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PIPE int…

• Multi-Protocol PHY
• In Production
• Immediate

A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.

• USB 2.0

A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization.

• Multi-Protocol PHY
• In Production
• Immediate

In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.

• Channel Coding
• In Production
• Immediate

On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.

• Channel Coding
• In Production
• Immediate
• Home Plug

1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…

• Single-Protocol PHY
• In Production
• Immediate

This GNSS RF Receiver IP is silicon-proven in TSMC40nm ULP process node, offers comprehensive support for all current satellite-b…

• GNSS
• In Production
• Immediate

This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to…

• Modulation Demodulation
• In Production
• Immediate
• Certified

Smart card controller core is compliant to ISO 7816 3 specification.

• Smartcard
• In Production
• Immediate
• Yes