T2M GmbH IP Cores

The Digital video broadcasting for cable systems systems, a FEC sub-system is needed.

• Channel Coding
• In Production
• Immediate
• yes

In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…

• Channel Coding
• In Production
• Immediate
• yes

In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.

• Channel Coding
• In Production
• Immediate
• yes

In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.

• Channel Coding
• In Production
• Immediate
• yes

The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…

• Channel Coding
• In Production
• Immediate
• yes

The BCH decoder has four main functional blocks along with memory blocks.

• Channel Coding
• In Production
• Immediate
• yes

The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling…

• Multi-Protocol PHY
• In Production
• Immediate

A physical layer IP for LVDS Receiver.

• Single-Protocol PHY
• In Production
• Immediate
• IEEE 1596.3 Standard

Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…

• Single-Protocol PHY
• In Production
• Immediate
• DisplayPort version 1.4 rec…

The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4.

• HDMI
• In Production
• Immediate
• HDMI 1.4 Receiver, HDCP rev…

IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY provides a…

• HDMI
• In Production
• Immediate
• HDMI 1.4 Transmitter

IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY supports p…

• HDMI
• In Production
• Immediate
• HDMI 1.4 Transmitter

MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol.

• MIPI
• In Production
• Immediate
• mipi_DSI_specification

The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.

• MIPI
• In Production
• Immediate
• MIPI CSI-2 Specification v1…

The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.

• MIPI
• In Production
• Immediate

A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…

• USB 3.1

The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with P…

• Multi-Protocol PHY
• In Production
• Immediate
• PIPE 4.3, PCIe 3.0 Base Spe…

A RF Transceiver (IP/die) for adding Bluetooth Low Energy v5.2 (2.4GHz) capability to any SoC with embedded MCU via a standard SP…

• TSMC
• 40nm
• G
• In Production

This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to…

• Modulation Demodulation
• Silicon Proven
• Ready to license
• Certified

It is a fully integrated dual-band transceiver IP for 802.15.4g and 802.11ah applications.

• RF Transceiver
• In Production
• Immediate
• IEEE