Vendor: T2M GmbH Category: Single-Protocol PHY

JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP

The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…

TSMC 55nm GP In Production View all specifications

Overview

The JESD 204B controller IP is highly optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, FPGA and ASSP technologies. The solution defaults provide line-speed up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The enables quick and reliable deployment of both the Transmitter (TX) and the receiver (RX) and comes optionally and tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP-core is Silicon proven heavily tested In UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions .

Key features

  • Widest feature set available in market.
  • Scrambling and de-scrambling Included.
  • High performance transport layer support.
  • Build in test functions
  • Silicon proven
  • Lint/CDC optimized
  • UVM regression tested
  • Interoperability tested with leading PHY/Serdes vendors
  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • Targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 55nm GP In Production

Specifications

Identity

Part Number
JESD204B Tx-Rx PHY IP in 65GP/55GP
Vendor
T2M GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

Learn more about Single-Protocol PHY IP core

Three Design Aspects you shouldn't miss while building an NB-IoT Protocol Stack

It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP?

JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP