Arasan Chip Systems Inc. IP Cores

Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.

• Single-Protocol PHY

The NAND flash controller IP provides easy, reliable access to an off-chip NAND flash.

• Controller

The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it.

• Controller

The NAND Flash landscape is changing and the NAND Flash Controller IP Core is changing in accordance with it.

• Controller + PHY

Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard.

• CAN / CAN-FD / CAN-XL

The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.

• SPI / QSPI XSPI

16-bit xSPI + PSRAM IP Solution including support for AP Memory's Xccela™ PSRAM and the latest LVpSRAM™

• SPI / QSPI XSPI

Arasan Chip Systems, the provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 IP.

• USB

Arasan Chip Systems, the provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 V2.0 IP.

• USB

The xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions.

• SPI / QSPI XSPI

The Universal Flash Storage 3.1 (UFS 3.1) is a simple but high-performance, serial interface primarily used in mobile systems, be…

• UFS Controller

Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface.

• UFS Controller

VESA introduced the first Display Stream Compression (DSC) standard in 2014.

• VESA DSC

VESA introduced the first Display Stream Compression (DSC) standard in 2014.

• VESA DSC

Arasan Chip Systems, the provider of IP for Mobile Storage Standards, presents its latest xSPI Master IP for access to NOR Flash …

• SPI / QSPI XSPI
• Silicon proven
• Compliant with Motorola, TI…

Arasan Chip System’s xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all condition…

• SPI / QSPI XSPI
• Silicon proven
• Compliant with Motorola, TI…

USB 1.1 Device The USB 1.1 Device IP Core is an USB 1.1 compliant device core with optional AHB, APB, PCI, or Custom bus interfac…

• USB

UFS 3.0 is the next specification update pending from JEDEC.

• UFS Controller

The NAND Flash landscape is changing and the Arasan NAND flash management technology is changing with it.

• Channel Coding

UFS 3.1 is the next specification update pending from JEDEC.

• UFS Controller