BCH ECC Core IP

The NAND Flash landscape is changing and the Arasan NAND flash management technology is changing with it. The increasing demand of lower cost but higher raw-bit-error rate NAND flash with higher data transfer rate and better data integrity of a Solid State Drive (SSD) has led to the need of high efficiency and high-performance ECC algorithm.

The patent-pending Dynamically Configurable BCH technology is the base for the BCH ECC engine incorporating BCH coders and decoders configurable for a wide range of code-length for high performance and high data rate error corrections. The BCH ECC engine with configurable code-length BCH coders and decoders performs the Inversion-less Berlekamp-Massey Algorithm (IBMA) to generate or decode the ECC code on each clock. With Arasan’s innovative code-length configurability from 1-bit to 32-bits of the BCH coders and decoders to meet the target NAND flash error correction requirements, the number of clocks to generate or decode the ECC codes are greatly reduced, thus increases the system performance. In addition, the configurable code-length matching the target NAND ECC requirement (eg. 24-bit) eliminates the unnecessary waste of ECC code storage area (i.e. NAND spare area) when compared to using fixed-bit (eg. 32-bit) ECC engine. Thus, Arasan NFC provides the flexibility to use NAND flash with smaller spare area, or to free up the spare area for other purpose.

Supporting MLC and SLC NAND with advanced process technologies, Arasan’s Dynamically Configurable BCH ECC engine IP addresses the needs of system architects and chip design teams designing electronics devices requiring high reliability and high bandwidth.