Arasan Chip Systems Inc. IP Cores

Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data s…

• UFS Controller

The RF Front End (RFFE) control interface is defined to offer a common Interface for controlling RF front-end devices.

• MIPI RFFE

Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers.

• MIPI RFFE

This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…

• MIPI D-PHY

This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…

• MIPI C-PHY + 1

The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself …

• Single-Protocol PHY

The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification.

• I2C / I3C

The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specificati…

• I2C / I3C

The I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specificati…

• I2C / I3C

The I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification.

• I2C / I3C

The CAN-XL Bus Controller Core performs serial communication as per CAN 2.0, CAN-FD & CAN-XL Specifications.

• CAN / CAN-FD / CAN-XL

The CAN-SEC Acceleration Engine Core implements the CAN-XL Protocol (CiA 610-1), CAN-XL Addon Part 1-Simple/Extercontent Indicati…

• CAN / CAN-FD / CAN-XL

The Controller Area Network – Flexible Data-Light (CAN-FD Light) Controller IP implements the CAN FD-Light (CIA 604-1) protocol.

• CAN / CAN-FD / CAN-XL

The SPMI Host and Device IP (Configurable Controller Cores) implements MIPI SPMI2.0 protocols.

• Power Management

Arasan’s xSPI/PSRAM interface PHY is designed to work with both the xSPI or PSRAM master host controller IPs.

• PHY
• XSPI

The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion…

• MIPI

This is a production-ready stack for Arasan’s eMMC Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.

• SD / eMMC Controller

The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stac…

• I2C / I3C

The eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50…

• High-Speed

The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.

• SPI / QSPI XSPI