Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PH…
- Verification IP
System peripheral IP cores are essential building blocks in modern SoC and ASIC designs, providing control, management, and support functions for the overall system operation.
This category includes a wide range of peripheral functions such as DMA controllers, interrupt controllers, monitoring and health management blocks, power management controllers, storage-related controllers, system controllers, and timers & watchdogs. These IP cores help coordinate data movement, system supervision, power optimization, fault detection, and overall platform management.
This catalog allows you to explore and compare system peripheral IP cores from leading vendors based on functionality, performance, power consumption, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, or industrial controllers, you can find the right peripheral IP to support your system architecture.
Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PH…
SD 3.0/SDIO 3.0/eMMC 4.51 Host Controller Software Stack
This is a production-ready software stack for Arasan’s SD 3.0/ SDIO 3.0/ eMMC 4.51 Host Controller IP that is used to connect to …
eMMC 4.51 Device Controller IP
eMMC 4.51 is the latest specification released by JEDEC and is designed to meet the requirements for secure yet flexible program …
SD 4.1 Hardware Validation Platform
The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile …
Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data s…
Controller IP for SD and eMMC interfaces including managed NAND devices
Centralised Network Configurator
Software solution targeting the configuration of Ethernet switches and endpoints in TSN networks Centralized Network Configurator…
Wrapper IP building blocks for ES1 IP
IP
Get to market faster with an error-free system memory map Accelerate large-scale SoCs schedules with effective hardware/software …
An easy-to-use, scalable, and fully automated process to capture IP description in IP-XACT format Magillem® Packaging uses a data…
A SoC integration solution to accelerate complex system design For design teams coping with exploding complexity and the need to …
GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation…
Direct Memory Access Controller
The DDMA is a four-channel Direct Memory Access Controller.
AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI…
AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
The DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI…
The DUTS stands for DCD’s Universal Timers System.
The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP p…
TSMC CLN12FFC Chip Performance Monitor
IGACPMV08A is an on-chip performance monitor which contains a maximum of 32 customized multiple ring oscillators.
TSMC CLN7FF Chip Performance Monitor
IGACPMX01A is an on-chip performance monitor which contains a maximum of 32 customized multiple ring oscillators.
TSMC CLN5FF Chip Performance Monitor
IGACPMY01A is an on-chip performance monitor which contains a maximum of 32 customized multiple ring oscillators.