Magillem Connectivity

A complete SoC integration solution to accelerate complex system design

For design teams coping with exploding complexity and the need to innovate quickly, the Magillem® 5 Connectivity product streamlines and shortens the integration process by 30% to create correct-by-construction platforms.

By accelerating IP deployment with continuous integration, Magillem Connectivity delivers a powerful automated hardware development flow adapting to changes and eliminating time spent on tedious tasks to focus on what matters most.

Reduce large-scale SoC designs integration from months to weeks

With a proven data model based on the IP-XACT industry standard, Magillem Connectivity enables:

• IP packaging for the efficient handling of all aspects of system integration for connectivity and configurability.
• Automatic IP instantiation and error-free connection process with a solid API to access all the design data.

Magillem 5 Connectivity allows a significant jump in productivity, predictability with progress reporting, and portability of the design environment. For very large designs with thousands of instances, it streamlines the integration process and helps decrease design cycle time by up to 30%.

Meet power and floorplan constraints with error-free design restructuring

Magillem Connectivity helps eliminate painful, manual steps across the build flow and optimize the time-consuming physical design netlist. It delivers automated hierarchy manipulation capabilities with built-in checks ensuring high-quality generated design.

• Separate RTL hierarchy and physical hierarchy enables powerful features, including feedthrough connections for abutted floorplan and hard macros replication.
• Rapid response to physical design requirements, reducing the process from weeks to 1 to 2 days.
• Drastic improvement in development time and SoC quality through continuous integration flow.

Generate error-free system maps

Full integration of Magillem Registers and Magillem Connectivity helps synchronize connectivity and memory map information:

• Calculate and display the system map from the selected initiator.
• Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
• Check that all the software visible elements (registers or memory regions) in connected targets are present in the memory map.

• Project management: Design navigation and data aggregation.
• Parameters configuration: Hierarchical propagation or overriding.
• SoC assembly: Bus i/f detection, rule-based connectivity, bus/signal split/tie/open, hierarchical connection, glue logic insertion, feedthrough.
• Hierarchy manipulations: Move, merge, and flatten a physical/virtual hierarchy for RTL restructuring/partitioning.
• Platform derivatives: With the incremental design, automatic update, and design diff and merge capability.
• Comprehensive checkers: Catch errors as you enter the design information before running any simulation.
• Advanced generation capability: RTL netlist generation, in addition to makefile scripts for an extensive range of EDA tools
• Tool integration: Tight link with the connectivity tool to generate a system address map when both tools are combined.

• True IP Reuse Methodology: IPs and subsystems with vendor-independent IP packaging (IP-XACT based) for reuse across design and design flows
• Shorten and streamline the IP integration process: Accelerate connectivity through automation
• Reduce iteration cycle time for integration of new IP versions, at any stage of the assembly
• Continuous Integration with a robust SOC build process: The solution is repeatable and scalable, allowing it to quickly react and adapt safely to meet changing design needs within a project or in the future
• Single Source of truth environment for system design: Empower efficient collaborative work between the design teams
• Enable interoperability between the steps of a complex design flow
• Correct-by-construction designs: Catch errors as you enter the design information before running any simulation thanks to the built-in checkers that ensure higher-quality designs
• Boost Productivity: Automation reduces the effort and rework, ensures repeatability and eliminates human errors for higher quality design and shorter time to market
• Leverage Technical Expertise: Reduce tedious and time-consuming tasks to focus on core business.