Vendor: Digital Blocks, Inc. Category: DMA

AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams

The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI…

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Overview

The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.

Descriptor Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interface, with resulting output Status on Status Stream, AXI4-Stream Interfaces.

The vendor offers two version releases of the DB-DMAC-MC2-CS-MM2S-S2MM:

  •  High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities.
  •  Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost

Key features

  • 2 Dedicated DMA Channels, 1 each for data transfers for the following:
    • MM2S: AXI4-Memory Map Read Data to AXI4-Stream Write Data
    • S2MM: AXI4-Stream Read Data to AXI4-Memory Map Write Data
  • Command and Status via AXI4-Stream Interfaces - 1 set per MM2S & S2MM:
    • Control input via Descriptor Command AXI4-Stream Interfaces
    • Status output via Status AXI4-Stream Interfaces
    • Commands & Status FIFOs for Queuing - Parameters for depth
  • MM2S & S2MM DMA Controllers:
    • Read & Write DMA Controller Engines
    • Data FIFO - Parameters for width and depth
    • Unaligned data transfers with byte realignment & using byte strobes
    • Releases versions supporting high or nominal AXI bandwidth throughput, with tradeoff in control plane VLSI resources and licensing cost
  • Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
  • Programmable Data Burst Capability: 1, 4, 8, 16 (fixed) and 1 – 256 (AXI4)
  • 4 KB boundary crossing detection & resizing of AXI transaction
  • Compliance with AMBA Specifications:
    • AXI4 Protocol Specification (Memory Map Read/Write Channels)
    • AXI4-Stream Protocol Specification
  • Fully synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Block Diagram

DB-DMAC-MC2-CS-MM2S-S2MM block diagram

What’s Included?

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Specifications

Identity

Part Number
DB-DMAC-MC2-CS-MM2S-S2MM
Vendor
Digital Blocks, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Digital Blocks, Inc.

Learn more about DMA IP core

DMA IP Integration

There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.

Moving to AMBA® 5? Your AMBA® 4 IP Can Still Come With You

As SoC architectures adopt AMBA® 5 fabrics and components, many proven IP blocks still rely on AMBA® 4 or earlier interfaces. That creates a common integration problem: how do designers connect newer AMBA® 5 system components to existing IP without redesigning the IP or replacing verified blocks?

Frequently asked questions about DMA IP

What is AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams?

AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams is a DMA IP core from Digital Blocks, Inc. listed on Semi IP Hub.

How should engineers evaluate this DMA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DMA IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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