Vendor: Arteris Category: System Controller

Magillem Packaging

An easy-to-use, scalable, and fully automated process to capture IP description in IP-XACT format Magillem® Packaging uses a data…

Overview

An easy-to-use, scalable, and fully automated process to capture IP description in IP-XACT format

Magillem® Packaging uses a data model based on the IP-XACT industry standard to handle all aspects of system integration for connectivity, configurability, and system memory map. It enables true IP reuse methodology with an interoperable design flow for complex SoCs, including register management, IP capture, and SoC IP assembly.

With a nonintrusive, scalable, and automatic process for legacy and new IP that enables seamless IP client portfolio packaging, Magillem Packaging delivers both data accuracy and flexibility. It allows incremental or full packaging with IP-XACT compliance and data consistency that are ensured by construction and assessed with a built-in Magillem IP-XACT checkers suite.

Key features

  • IP-XACT 2022 support​
  • HDL import: Verilog, SystemVerilog​
  • Static elaboration support (with resolved configurations)​
  • FileSet elaboration with full source file documentation​
  • Bus interface automatic mapping of physical ports​
  • Memory map intent capture​
  • Catalog management​
  • IP-XACT compliance checkers suite​

Block Diagram

Benefits

Correct by construction IP-XACT description

Improved quality without requiring any prerequisite IP-XACT expertise.

True IP reuse methodology

Ideal for IP and subsystems with vendor-independent IP packaging (IP-XACT based).

Single source-of-truth environment for system design

Enables multipurpose usage and helps ensure data consistency for design tasks and teams.

Specifications

Identity

Part Number
Magillem Packaging
Vendor
Arteris
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: United States

Learn more about System Controller IP core

Ten reasons interconnect matters

Interconnect is the Rodney Dangerfield of IP blocks. It gets no respect. It connects hundreds of disparate IP blocks, each with hundreds of interface signals, and dozens of transaction protocol attributes. It does it in a way that each IP need not know the protocol details of any other. It also provides for the data access requirements of each IP, and does it physically distributed across the chip floorplan. Interconnect fabric technology is sophisticated, and very important for modern chip designs. Following are ten reasons why interconnect matters.

Arteris System IP Meets Arm Processor IP

The design of system-on-chip (SoC) devices for automotive applications—and the reuse of portions of those designs for future SoC incarnations—just got a lot easier with the recent announcement of the expanded partnership between Arm and Arteris.

Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs

On March 24, the 2026 XuanTie RISC-V Ecosystem Conference, hosted by Alibaba DAMO Academy, was held in Shanghai. Hundreds of industry and academic institutions from around the world—including Qualcomm, Arteris, Canonical, SHD Group, Haier, and ZTE—gathered to share cutting-edge practices in RISC-V.

Re-Architecting SoCs for the AI Era

This paper will define AI, describe its applications, the problems it presents, and how designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design. It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product

This paper explains the changes in the role of the semiconductor industry in the automotive supply chain and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.

NoC Interconnect Fabric IP Improves SoC Power, Performance and Area

Imagine you have defined the structure of a system-on-chip and now you have to assemble all the IP blocks and make them communicate on the die. You have spent months rigorously selecting SoC IP that reflects the desired chip functionality. However, without the on-chip interconnect fabric it is just a collection of isolated blocks.

Frequently asked questions about system controller IP cores

What is Magillem Packaging?

Magillem Packaging is a System Controller IP core from Arteris listed on Semi IP Hub.

How should engineers evaluate this System Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this System Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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