Magillem Registers

Get to market faster with an error-free system memory map

Accelerate large-scale SoCs schedules with effective hardware/software interface development

Magillem® Registers offers a single source of truth methodology, which not only targets the traditional need to manage registers, but also addresses today’s hardware and software integration challenges for large-scale SoCs.

Quick and scalable automated implementation with Magillem Registers helps cut time to market in half for hardware/software interface (HSI) generation.

Straightforward register intent capture

Magillem Registers translates register specifications into executable design code by automatically importing the register descriptions from different sources and formats.

• Automatically checks the accuracy of the information (overlaps, configurability, reserved empty spaces, …).
• Enables close collaboration between hardware, software, and tech doc teams through a single source of truth methodology for consistently generated data.
• Comprehensive HSI automation helps ensure improved quality design and increased productivity.

Automatically generate consistent data

Magillem Registers is a true cross-compiler with over 1,000 functional, behavioral, syntactic, and semantic error checks. It supports various formats and generates multiple outputs simultaneously.

Generated data is consistent and complete, which gives verification teams an up-to-date generated register model to work from.

Error-free system map generation

Full Magillem Registers and Magillem Connectivity integration synchronizes connectivity and memory map information:

• Calculate and display the system map from the selected initiator.
• Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
• Check that all the software visible elements (registers or memory regions) in connected targets are present in the memory map.

• Single database: Import and capture memory map information into a single database for generating RTL, digital verification, firmware, and documentation.
• Various input formats: Provides for CSRSpec language, SystemRDL, IP-XACT 2009/2014/2022, spreadsheets, and more.
• Extensive error/syntax checking: More than 1,000 error checks.
• Alternative UVM backdoor methodology: Supports high performance on large designs.
• Advanced features: Registers broadcast/alias, virtual registers, wide memories and atomic access support.
• Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined.

Easy specification adjustment

Rapid iteration with updated information across design teams helps ensureg data consistency.

Agile design process

Clearly defined process to ensure best practices and early engagement of the entire design team.

Scalable and expansive

Compiles over 5 million registers and can be used on large-scale SoC memory maps.

Automated and efficient

Helps reduce tedious and error-prone tasks with a fully automated flow, and shortens the overall process.

Accurate and consistent

Hardware, software and documentation are all in sync to ensure accuracy and cross-team consistency through a single source of truth.

Quality assurance

Catch errors at the data entry stage with the memory map information before running any simulation.

Productivity booster

Accelerate the schedule with a correct-by-construction software interface.