Vendor: Siemens Digital Industries Software Category: UFS Controller

Verification IP for UFS

Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PH…

Verification IP View all specifications

Overview

Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PHY

Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.

With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work more on verifying both low-level and system-level functions.

Avery compliance test suites offer effective core-through-chip-level tests, includ ing those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.

Key features

UFS VIP is a comprehensive VIP solution portfolio for SoC and IP designs incorporating the UFS Host Controller (UFSHCI), UFS 4.0, and UME standard, in conjunction with the MIPI Unipro and M-PHY standards.

  • UFS host supported two ways:
    • UFSHC 4.0 driver model supports UME 1.0 and implements UFSHCI programming interface, including host adapter to various host bus interfaces, including AMBA AXI and AHB
    • Generic host model emulates UFSHC host driver and  UFSHCI-based controller
  • UFS device model emulates simple UFS device, including sparse logical block storage and processes over 20 SCSI
  • Supports command sets: Native UFS and SCSI SPC-4, SBC-3, and SAM-5
  • Supports UFS DME and CPort users
  • CPort adapter interfaces to Avery or third party UniPro IP/VIP, enabling mix and match between UFS and Unipro layers to support module-level integration and verification
  • M-PHY model
  • Support draft M-PHY 5.0 Multiple LANE provisions
  • Multiple transmission modes include LS-MODE NRZ and PWM signaling Multiple power saving modes
  • Support error injections (encoding, disparity, etc.)
  • UniPro model
    • Emulates UniPro draft 2.0 protocol stack layers and M-PHY
    • Supports all service primitives (SAP) and service data units (x_SDU)
    • DME user supports all sequences of control, configuration,  and status primitives
    • Transport service
    • Allocates connections between CPorts
    • Schedules message transfers between CPort users
    • Supports CPort signal interface
  • Supports UniPro test feature
  • Inject errors at all layers through callbacks
  • Comprehensive assertions track UFS and MIPI compliance coverage
  • Functional coverage tracks range of packet traffic, FSMs, and complex operational sequences
  • Tracker log monitors all levels and improves debug
  • Comprehensive directed and constrained random compliance test suite for UFSHCI and UFS device achieves high protocol coverage

Block Diagram

Avery Verification IP for UFS block diagram

Benefits

  • Provides effective core-through-chip-level tests
  • Develops more complex tests
  • Enables focusing on verifying low-level and system-level functions
  • Isolates compliance issues

Specifications

Identity

Part Number
Avery Verification IP for UFS
Vendor
Siemens Digital Industries Software
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about UFS Controller IP core

What's The Best Way to Verify Your SSD Controller?

To handle the complexity of hardware and software for advanced SoCs, design teams are employing hardware emulation for full chip functional verification of the controller SoC design as well as for the SoC's firmware.

Use test data to diagnose failed memory

Here's a common situation for memory designers: your RAM or flash has been fabricated, but the yield is lower than you would like. Maybe there is an odd correlation between a particular failure mode and your manufacturing process, but you'll need solid data to track down the yield limiter. The only information you get from the tester is pass/fail, so it doesn't really help you to identify the root cause.

Design clock controllers for hierarchical test

Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation memory requirements, and put the ATPG process much earlier in the design cycle than other methods. In hierarchial test, users need to add scan wrappers to blocks so the blocks can be treated as independent plug-and-play blocks with plug-and-play patterns.

Apply memory BIST to external DRAMs

3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional, single-die embedded SRAM implementations.

Guidelines for Successful SoC Verification in OVM/UVM

With the increasing adoption of OVM/UVM, there is a growing demand for guidelines and best practices to ensure successful SoC verification. This paper will first describe the basic tenets of OVM/UVM, and then it tries to summarize key guidelines to maximize the benefits of using state of the art verification methodology such as OVM/UVM.

Frequently asked questions about UFS Controller IP

What is Verification IP for UFS?

Verification IP for UFS is a UFS Controller IP core from Siemens Digital Industries Software listed on Semi IP Hub.

How should engineers evaluate this UFS Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UFS Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP