The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP p…
The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP products. The I8500 supports the RVB23 profile of the RISC-V base ISA and mandatory extensions, plus a number of optional RISC-V extensions. It also includes further enhancements for a variety of functions and operations through MIPS-Defined Instructions (MDIs), a set of custom instructions provided as an extension from MIPS to the standard RISC-V ISA and related features.
The MIPS® I8500 Multiprocessing System (MPS) provides a highly scalable foundation for designing and building the types of cores required to handle the compute and data movement intensive tasks in high reliability, enterprise class systems, such as:
The I8500 MPS scales to 64 heterogeneous clusters of multi-threaded multi-core MIPS CPUs, using an ACE (AMBA® Coherent Extensions) interface at the cluster level to the system. This interface can also enable integration and coherent operation with heterogeneous processing units such as GPUs and accelerators at the System-on-Chip (SoC) level.
The I8500 is designed to provide best in class efficiency for highly parallel data processing and data movement operations common to both hardware multithreading per core, and scalabililty up to many core systems in groups of connected coherent clusters. Each core can be implemented with up to 4 hardware threads (harts) in a 9-stage triple issue in order microarchitecture. Within a cluster, the I8500 Coherence Manager (CM) maintains cache coherency between all cores, main memory, and I/O devices, as well as coherency over the system interface with other clusters.
The I8500 MPS is a configurable and synthesizable solution. The collection of clusters of cores can be configured with a variable number of cores, I/O coherent interfaces, and L2 cache size, along with other interfaces, interrupts, and debug/trace support. At the individual core level, each core can be configured with L1 cache sizes, optional inclusion of ScratchPad RAMs (SPRAMs) for Data or Instructions, and number of harts per core.
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Data Movement Engine - Efficient data-processing and simultaneous multi-threading, low latency and deterministic data access is a DMA IP core from MIPS listed on Semi IP Hub.
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