ISO 7816 Based Smart Card Reader
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications.
- Smartcard
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
ISO 7816 Based Smart Card Reader
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications.
The DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO)…
LIN Bus Controller – Basic and Safety-Enhanced
DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability.
I2C Controller IP – Master, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
The DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus …
GDA's USB 3.0 SSIC controller is a configurable core and implements the USB 3.0 SSIC functionality that can be interfaced with th…
DSI transmitter controller for application
I2C Controller IP – Master / Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses
The DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus…
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
Small is beautiful...
Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
The DQSPI is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory.
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390.
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps.
Mobile Phase Recovering Equalizer
The Mobile Phase Recovering Equalizer (MPRE) FPGA core combines Channel Equalization, Phase Recovery, and Symbol Slicing in a sin…
The RapidlO-AXI Bridge (RIO-AXI Bridge) is a flexible and configurable IP used along with the native RapidlO Controller (GRIO) to…
The 10/100/1000Mbps Tri-mode Ethernet MAC offers an IEEE802.3-2008 compliant solution that meets the requirements for tri-mode LA…
Certified USB 5G & 10G Dual Mode Controller
USB 5G, 10G Dual Mode controller is a configurable core and implements the USB Host functionality or USB Device functionality sel…
I2C Controller IP – Master, Parameterized FIFO, AXI Bus
The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Master, Parameterized FIFO, AHB Bus
The DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mo…
I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…