DCD-SEMI Introduces eSPI Combo for Next-Generation Intel-Based Platforms
DESPI eSPI Controller IP Core and DESPI eSPI IP Core Target deliver a complete, high-speed eSPI interface solution for FPGA and ASIC designs.
Vendor:
Digital Core Design
Category:
HDLC
HDLC/SDLC controller
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390.
Overview
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter.
Key features
- Two separate receiver and transmitter interfaces.
- Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing
- Address recognition for receiver and address insertion for transmitter
- Two or one byte address field
- RC-16 and CRC-32 computation and checking
- Collision detect
- Byte alignment error detection
- Programmable number of bits for idle detection
- NRZI coding support
- Shared flags, shared zeros support
- Pad fill with flags option
- Transmitter clock generation
- 8-bit CPU interface
- Interrupt output for handling control flags and FIFOs’ filling
- Configurable core parameters Â
Applications
- http://www.dcd.pl/ipcore/102/d6802/
What’s Included?
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Specifications
Identity
Part Number
DHDLC
Vendor
Digital Core Design
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Poland
Learn more about HDLC IP core
DCD-SEMI expands CryptOne with EdDSA Curve25519 IP core for secure embedded systems
DCD-SEMI introduces a new CryptOne extension supporting EdDSA25519 signatures and X25519 key exchange, delivering high security, low latency, and efficient hardware implementation for modern SoC and FPGA designs.
DI3CM-HCI, A High-Performance MIPI I3C Host Controller IP Core for Next-Generation Embedded Designs
DCD-SEMI, a provider of silicon-proven IP solutions, announces the availability of the DI3CM-HCI, an advanced MIPI I3C Host Controller Interface (HCI) IP Core designed to modernize peripheral connectivity in embedded, IoT, consumer, and industrial systems.
DCD-SEMI Unveils Ultra-Fast DAES IP Core for AES Encryption
DAES IP Core is a high-performance solution that accelerates AES encryption and decryption for modern secure systems. Supporting 128- and 256-bit keys across multiple modes—including ECB, CBC, CFB, OFB, and CTR—DAES delivers ultra-fast throughput and easy integration.
DCD-SEMI Brings Full ASIL-D Functional Safety to Entire Automotive IP Cores Portfolio
DCD-SEMI today announced that its complete automotive IP Cores family — including Classical CAN, CAN FD, CAN XL but also LIN, PSI5 and SENT —is now available as Safety Element out of Context for ISO 26262 functional safety up to ASIL-D, the highest Automotive Safety Integrity Level.
DCD-SEMI Joins MIPI Alliance and Unveils Latest I3C IP at MIPI Plugfest Warsaw 2025
Joining MIPI Alliance marks a significant step in DCD-SEMI’s commitment to delivering industry-compliant, high-performance IP cores to its global customers. As part of this initiative, DCD-SEMI will showcase its latest I3C IP core during the upcoming MIPI Plugfest, held in Warsaw on June 23-24, 2025.
Frequently asked questions about HDLC IP cores
What is HDLC/SDLC controller?
HDLC/SDLC controller is a HDLC IP core from Digital Core Design listed on Semi IP Hub.
How should engineers evaluate this HDLC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HDLC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.